(1) Field of the Invention
The invention relates to processes for the manufacture of semiconductor devices and more particularly to processes for forming capacitors in conjunction with the formation of self-aligned-polysilicon-gate field effect transistors.
(2) Background of the Invention and Description of Prior Art
Complimentary metal oxide semiconductor(CMOS) field effect transistor(FET) technology involves the formation and utilization of n-channel MOSFETs(NMOS) and p-channel MOSFETs(PMOS) in combination to form low current, high performance integrated circuits. The complimentary use of NMOS and FPMOS devices, typically in the form of a basic inverter device, allows a considerable increase of circuit density of circuit elements by reduction of heat generation. The increase in device density accompanied by the shrinkage of device size has resulted in improved circuit performance and reliability as well as reduced cost. For these reasons CMOS integrated circuits have found widespread use.
Many integrated circuit designs include capacitors, the formation of which must be incorporated into the manufacturing process. In the manufacture of dynamic random access memory (DRAM) integrated circuits, a number of processing steps are included in the process sequence which are dedicated exclusively to the formation of the memory cell storage capacitor. Other capacitors, are used in certain logic circuits, in peripheral memory support circuits, and in mixed-mode circuits. These capacitors can be formed simultaneously with the formation of the MOSFETs without requiring additional processing steps. Such capacitors utilize the same layers which are used to form the MOSFETs. Because they are simultaneously formed, they are also easily incorporated into the MOSFET interconnection circuitry.
A well known mixed mode integrated circuit includes a tungsten polycide-to-polysilicon capacitors and a CMOS device with a polycide gates. The devices are shown in cross section in FIG. 1. The MOSFET 12 is formed over an active area on a silicon wafer 20 and is isolated by a field oxide 22. The gate electrode 24A is formed of a polycide layer, which comprises a lower portion of polysilicon and an upper portion of a refractory metal silicide. The upper silicide layer improves the overall conductivity of the electrode. The polysilicon and the superjacent silicide layers are deposited by low temperature chemical vapor deposition (LPCVD). A preferred silicide is tungsten silicide(WSi.sub.x) which is formed over the polysilicon layer by the reaction of SiH.sub.4 with WF.sub.6. The MOSFET 12 is provided with the well known LDD(lightly doped drain) structure 30 which is formed by the use of sidewalls 26.
In another region of the wafer 20 a capacitor 14 is formed over a region of field oxide 22. The lower plate 24B is patterned in the same polycide layer as the gate electrode 24A. The dielectric material of the capacitor 14 is formed of a silicon oxide layer 32 which is also deposited by LPCVD using silane (SiH.sub.4) or dichlorosilane(SiCI.sub.2 H.sub.2) and N.sub.2 O or O.sub.2 as precursors. Oxide layer 32 is a component of an inter-poly-oxide(IPO) layer through which contact to the MOSFETs are formed. The upper electrode plate 34 of capacitor 14 is patterned in a second layer of doped polysilicon in which interconnective conductive links to the MOSFETs are also formed.
A problem occurs when the capacitor the dielectric layer 32 is deposited over the WSi.sub.x lower plate 24B. During formation of the WSi.sub.x, some of the product gases including fluorine are retained in the WSi.sub.x layer. During the initial stage of deposition of the oxide layer 32 which takes place at a temperature of about 800.degree. C., the WSi.sub.x layer out gasses into the oxide layer, forming gas pockets which degrade the dielectric layer by lowering its capacitance. WSi.sub.x outgassing can reduce the capacitance by as much as 10%. The degradation of the dielectric also presents a reliability concern.
The outgassing of tungsten silicide layers is well known. Chu et.al., U.S. Pat. No. 5,434,096 cites the delamination of a dielectric layer deposited over tungsten polycide gate electrodes caused by outgassing of the tungsten silicide. An anneal in an inert gas and oxygen at 900.degree. C. is applied after patterning of the polycide gate electrodes. An additional 20 minute anneal in vacuum or inert gas at 800.degree. C. is performed after BF.sub.2 + implantation of p-channel devices. These annealing steps are sufficient to prevent delamination. However, experiments by the present inventors have shown that such annealing steps are ineffective in eliminating capacitance degradation of the polycide/oxide/polysilicon capacitor.
Seita et.al., U.S. Pat. No. 5,527,718 cites a method for removing impurities, in particular fluorine, from polycide electrodes by heat treatment at temperatures between 450 and 800.degree. C. It was found that the anneal which was used to activate the polysilicon dopant at temperatures above 700.degree. C. caused fluorine embedded in the tungsten silicide to migrate and pile up at the subjacent polysilicon-gate oxide interface, thereby promoting enhanced oxidation of the gate oxide. A lower temperature anneal prior to the activation anneal drove out sufficient fluorine to alleviate the gate oxide problem. The preliminary anneal is performed at a temperature no less than the electrode formation temperature and no higher than the growth temperature of the gate insulating film.
Lur et.al., 5,668,394 also addresses fluorine induced gate oxide degradation by introducing a conducting barrier layer of TiN between the tungsten silicide layer and the gate polysilicon layer thereby preventing the migration of fluorine towards the polysilicon/gate oxide interface.
Kwasnick et.al., 5,273,920 shows a method of fabricating an amorphous silicon inverted thin film transistor using a hydrogen plasma treatment of the gate dielectric(silicon nitride) prior to the deposition of the amorphous silicon. Both depositions and the intermediate plasma treatment are advantageously applied successively in the same reactor without breaking vacuum. However, vacuum may be broken after the deposition of the dielectric and before the plasma treatment. The hydrogen plasma improves the effective mobility of carriers in the semiconductor layer.